The present invention relates to capacitors and more particularly, to large value integrated circuit capacitors embedded within a substrate and connectable to other electronic components.
In the microwave frequency spectrum, small and medium power solid state amplifier circuits are increasingly gaining prominance due to the longer life, smaller size and lower power consumption of the solid state devices. A common arrangement is for solid state devices, e.g. discrete gallium arsenide (GaAs) Schottky barrier gate field effect transistors (FETs) which are mounted on an insulating substrate, to be interconnected with discrete inductors, resistors, capacitors, and transmission lines. However, increased gain-bandwidth product and lower manufacturing costs accrue by further integrating these microwave discrete devices into monolithic devices wholly fabricated on gallium arsenide or other suitable semiconductor material. Examples in the prior art of production of integrated circuit passive devices is shown in U.S. Pat. Nos. 3,387,286, 3,745,430 and 3,138,744 for integrated circuit capacitors, 3,390,012 for integrated circuit capacitors and inductors produced on a substrate of yttrium iron garnet, and 4,065,742 for integrated circuit resistors.
Because of its superior high frequency capability, gallium arsenide is the preferred semiconductor material for microwave devices; however, on GaAs chips, space is particularly at a premium. At microwave frequencies, the optimum input impedance of medium power FETs is usually low, e.g. less than five ohms, thereby necessitating comparatively large interconnecting capacitors, e.g. more than five picofarads (pf). Integrated circuit capacitors as shown in the above cited patents having silicon dioxide (SiO.sub.2) or aluminum dioxide dielectrics must be at least 2500A.degree. thick to avoid pin hole short circuits between plates and have a production yield of 96 percent or better. Since the larger the distance between the capacitor electrodes the lower the capacitance value, a larger area on the chip for larger plate area is required to achieve the required capacitance value. A 5 pf capacitor of silicon dioxide dielectric requires a chip area of 0.016 mm.sup.2 (25 mil.sup.2) which is comparatively large. Additionally, the silicon dioxide dielectric is typically obtained by oxidation of silane at 390.degree. C. which places severe constraints on the processing cycle of the GaAs wafer at 390.degree. C. which is above the eutectic point of several of the metallizations required on the chip. RF sputtering of the SiO.sub.2 dielectric creates even higher temperatures. Room temperature anodization of aluminum or tantalum metal capacitor electrodes at 120 volts in a 3 percent tartic acid solution with a PH of 5.5 is a marginal process since there is still a considerable problem with pinhole short circuits between the electrodes.
U.S. Pat. No. 4,156,249 to Koo shows an interdigitated capacitor on a substrate surface but requires a large area to develop a large value of capacitance as discussed above. U.S. Pat. No. 3,962,713 to Kendall et al, while increasing the capacitance value per area, requires a highly doped, low resistivity substrate which requires a separate diffusion for the substrate to achieve this low resistivity, requires one plate of the produced capacitor because of the low substrate resistivity to be connected to ground thereby preventing its use as an input capacitor, and requires that the dielectric be deposited in a separate step as the substrate material cannot be used as an insulating dielectric due to the low resistivity, said deposited dielecric also being subject to the deficiencies discussed above. Thus, the capacitor of Kendall et al does not meet the present requirements.
U.S. Pat. No. 3,565,807 to Severisen et al shows a capacitor with plates formed in an insulating material such as aluminum oxide in the form of sapphire. An insulating substrate would require a number of deposition and diffusion steps for providing other hybrid components such as transistors on the same substrate. Additionally, the thermal conductivity of sapphire requires application of substantial localized power when burning out the grooves by the electron beam thereby causing the immediate substrate material to be damaged. Additionally, according to Severisen et al, 2.54 .mu.m is the minimum spacing that can be achieved between plates of the capacitor and such a capacitor would require a substantially larger amount of chip area for the value of capacitance of the present requirement, i.e. 5 pf. Such a 5 pf capacitor would require such a large area that when used at microwave frequencies, the capacitor may exhibit transit time effects, i.e. the time required for the electrical wave to traverse the capacitor would be a substantial percentage of the wave period.
Accordingly, it is desirable to produce a high value integrated circuit capacitor using a minimum chip area wherein the capacitor is substantially immune to pin hole short circuits in production and has a correspondingly high production yield. It is further desirable to produce a high value integrated circuit capacitor which requires a minimum of diffusion and depositing steps and is disposed on a high resistivity semiconductor substrate material to isolate the capacitor from other components thereby permitting both plates of the capacitor to be connected as desired to provide flexibility of wiring the capacitor into a circuit.